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Home > Archives > Volume 20, No 7 (2022) > Article

DOI: 10.14704/nq.2022.20.7.NQ33073

Design and FPGA Implementation of High-Speed Cryptographic System for Wireless Communications Based on Multi-Dimensional Hyperchaotic Generator

Hayder Mazin Makki Alibraheemi, Qais Al-Gayem and Ehab AbdulRazzaq Hussein


In this paper, the design and Field Programmable Gate Array implementation of a new algorithm for image encryption systems based on stream cipher using multi-dimensional hyperchaotic generators. In this new algorithm three different hyperchaotic generators are combined together to generate new Pseudo-Random bit generator to be used for image pixels masking (encryption). Four dimensional, six dimensional, and seven dimensional hyperchaotic generators are combined together using XOR operation to generate the new random bit stream. The hyperchaotic dynamical equations are solved by using Forward Euler integration method. The X-dynamics of each hyperchaotic system has been converted to binary stream. The binary streams are combined to generate the random bits generator to be used for encryption. The proposed system is tested for different image sizes (64×64, 128×128, 176×144, 256×256, and 2500×1875). The proposed system shows perfect encryption performance. Different randomness tests and security analysis are used to analyze the proposed encryption system such as, histogram, mean square error (MSE), peak signal to noise ratio (PSNR), NPCR, UACI, entropy, correlation coefficients and key space. FPGA Co-Simulation based on Xilinx PYNQ-Z1 zynq xc7z020 board is used to test the reality of the proposed image encryption algorithm. The simulation and implementation results proof the strength, robustness and speed of the proposed algorithm. The results proof that the proposed algorithm is suitable for stream cipher-based image encryption systems and outperforms similar encryption algorithms


Cryptography, Hyperchaos systems, Image Encryption, FPGA Hardware Co-Simulation, Xilinx system generator, Stream Cipher

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